In-situ doped and tensily stained ge junctionless gate-all-around nFETs on SOI featuring Ion = 828 µA/µm, Ion/Ioff ∼ 1×105, DIBL= 16–54 mV/V, and 1.4X external strain enhanceme

In-situ CVD doping and laser anneal can reach [P] and tensile strain as high as 2×10²⁰ cm^-3 and 0.34%, respectively, in Ge on SOI with low defect density and high activation rate (nearly 100% near the surface), and enables high performance of the junctionless (JL) Ge gate-all-around (GAA) nFETs. The device with the W_fin of 13 nm, EOT of 10 nm, and nominal L_G of 280 nm has I_on = 350 μA/μm, I_on/I_off = 3×10⁶, SS = 185 mV/dec, and DIBL = 16 mV/V. The device with the W_fin of 9 nm and EOT of ~ 0.8 nm achieves the record high I_on of 828 μA/μm at V_GS - V_T = 1.5 V and V_DS = 2 V with DIBL = 54 mV/V, I_on/I_off = 1×10⁵ and SS = 150 mV/dec. Besides the epitaxial tensile strain (0.34%) generated by laser anneal due to the misfit of thermal expansion coefficients between Ge and Si, the enhanced tensile strain by the microbridge structure is also beneficial for I_on. The drain current enhancement of ~40% is achieved under the mechanical uniaxial tensile strain of ~0.25% due to sub-band splitting and carrier repopulation into the L4 valleys with the small conductive effective mass. The non-uniform shape of Ge channel with a minimum width at the center leads to enhanced I_on as compared to uniform channel. The extracted mobility of JL devices increases with increasing temperature, indicating the domination of impurity scattering. The threshold voltage of JL devices has the negative temperature coefficient and EOT scaling reduces the temperature dependence.