Sub-60 mV/decade steep transistors with compliant piezoelectric gate barriers

A novel mechanism is proposed for transistors that exploits the negative differential capacitance of piezoelectric gate barriers. Electric field induced electrostriction modulates the thickness of a piezoelectric barrier. Piezoelectricity and electrostriction in a compliant piezoelectric barrier combine to provide negative differential capacitance (NDC) with internal charge amplification. The effect of the NDC in the gate capacitor of a FET is to boost the on-current, and to provide an opportunity for switching steeper than the 60 mV/decade Boltzmann limit, both highly desirable.