Perspective of tunnel-FET for future low-power technology nodes

Tunnel-FETs (TFETs) promise a subthreshold swing (SS) smaller than 60mV/dec and are considered as interesting candidates to replace MOSFET in future low-power technology nodes. The road ahead is challenging, with large discrepancy between experiment and prediction, the latter showing extremely promising performance for heterostructure TFET at small supply voltage Vdd. This paper starts with a calibration of the band-to-band tunneling (BTBT) models. It then discusses architecture and material optimizations, highlights the differences between n-TFET and p-TFET, and focuses on unexplored material aspects, like the decrease of dielectric constant with confinement. Parasitic effects are briefly touched upon, with trap-assisted tunneling (TAT) being the most challenging TFET parasitic to overcome. A new metric, VTAT, is defined to capture the TAT impact.