Title :
Ultra low contact resistivity (< 1×10−8 Ω-cm2) to In0.53Ga0.47As fin sidewall (110)/(100) surfaces: Realized with a VLSI processed III–V fin TLM structure fabricated with IIIȁ
Author :
Lee, Rinus T. P. ; Ohsawa, Y. ; Huffman, C. ; Trickett, Y. ; Nakamura, G. ; Hatem, C. ; Rao, K.V. ; Khaja, F. ; Lin, R. ; Matthews, K. ; Dunn, K. ; Jensen, A. ; Karpowicz, T. ; Nielsen, Peter F. ; Stinzianni, E. ; Cordes, A. ; Hung, P.Y. ; Kim, D.-H. ; Hi
Author_Institution :
SEMATECH, Albany, NY, USA
Abstract :
We report a record low contact resistivity of sub-1.0×10-8 Ω.cm2 realized on n+ In0.53Ga0.47As fin sidewall surfaces. This is achieved with VLSI processed fin TLM structures on wafer scale III-V on Si substrates. A novel low-damage III-V fin etch was developed and fins down to 35 nm were fabricated. A surface treatment to smoothen the fin sidewall surfaces was proposed, which reduced sidewall surface roughness variation by 90%. Additionally, we show for the first time that implant temperature could be used to eliminate implant damage in III-V fins. This increased activation efficiency (+3.6×) and reduced sheet resistance (-60%).
Keywords :
CMOS integrated circuits; III-V semiconductors; VLSI; elemental semiconductors; gallium arsenide; silicon; surface treatment; III-V fin TLM structure; In0.53Ga0.47As; Si; VLSI; fin sidewall surfaces; size 35 nm; surface treatment; ultra low contact resistivity; wafer scale III-V; Implants; Metals; Resistance; Rough surfaces; Silicon; Surface roughness; Surface treatment;
Conference_Titel :
Electron Devices Meeting (IEDM), 2014 IEEE International
DOI :
10.1109/IEDM.2014.7047155