A novel list-scheduling algorithm for the low-energy program execution

Author

Sinevriotis, G. ; Stouraitis, T.

Author_Institution

Dept. of Electr. & Comput. Eng., Patras Univ., Greece

Volume

4

fYear

2002

fDate

6/24/1905 12:00:00 AM

Abstract

This paper presents a novel list-scheduling algorithm for low-energy software execution. The aim of the instruction scheduling is the minimization of the inter-instruction energy costs that are due to the switching activity of the processor circuit. The input of the scheduling algorithm is the original code sequence. Its output is a re-arranged sequence of the same instructions that minimizes the total inter-instruction effect cost and that has no impact on the program functionality. The inter-instruction effect cost is determined by means of physical measurements. The target architecture has been the ARM7TDMI processor core. The results of the optimization algorithm have been validated upon the implementation of the IEEE 802.11 protocol microcode for wireless local area networks.

Keywords

VLSI; low-power electronics; microprocessor chips; optimisation; processor scheduling; ARM7TDMI processor core; IEEE 802.11 protocol microcode; instruction scheduling; inter-instruction energy costs minimization; list-scheduling algorithm; low-energy program execution; low-energy software execution; low-power design; optimization algorithm; register renaming; wireless LAN; wireless local area networks; Application software; Costs; Embedded software; Embedded system; Hardware; Minimization; Power dissipation; Scheduling algorithm; Software algorithms; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on

Print_ISBN

0-7803-7448-7

Type

conf

DOI

10.1109/ISCAS.2002.1010398

Filename

1010398