Investigation of strain rate effect on lifetime performance of wafer level CSP under different thermal cycling loading rate

Solder joints are commonly used in the electronic packaging industry to provide electrical connection and serve as the mechanical support between a package and a printed circuit board (PCB). A coefficient of thermal expansion mismatch between component and board generates thermally induced strains in solder joints because of environmental temperature change, which ultimately causes fatigue failure. The reliability of solder joints is a primary subject. One of the common solder failures is the formation of fatigue crack at the interface between solder joints and component under accelerated tests by subjecting electronic assemblies to temperature cycling. Lead-free solder materials have a high homologous temperature, and the damage mechanism induced by creep failure should be considered. Accelerated thermal cycling (ATC) has been widely used in the microelectronics industry for reliability assessment. ATC decreases life cycle test time through different means, such as increasing the ramp rate or decreasing the dwell time. Fast temperature cycles can reduce the test time, but the effects of ramp rate causes a variation in material properties because of strain rate and stress change. However, JEDEC did not impose strict requirements in selecting an optimum temperature profile for temperature cycling, and previous inconsistent test temperatures may affect the reliability assessment of the solder joints. This study used linear temperature-dependent Young´s modulus and Garofalo-Arrhenius creep equation to describe the solder deformation response. With the use of empirical Darveaux-based equations, the optimized mesh size in finite element model calculation was studied to accommodate the strain rate effect with different ramp rates.