TCBNCP process impact on package warpage performance

In recent years, the wafer nodes of semiconductor are getting smaller and narrower. In the view of the development trends in the semiconductor & semiconductor packaging technologies, the higher signal LO pin counts and thinner package are wide-spread applied on consumer electronics products (ex: Smartphone, Tablet devices or Digital cameras) as well as high performance network systems and high-end servers. Also, the package on Package (PoP) was developed to integrate the logic and memory devices via solder joint which combine the benefits of traditional packaging with the benefits of die-stacking techniques and the most obvious one is motherboard space savings. However, there will be a high possibility of yield drop issue during surface mount process and to guarantee the potential reliability of the solder joint between the top and bottom package. Consequently, the package warpage is one of the primary thermo-mechanical reliability concerns and challenge in semiconductor industry. This paper presents a systematic study on package warpage behavior. There are two bare die devices in 14 × 14mm² and 15 × 15mm² package size was selected for two kinds of assembly methods (traditional mass reflow (MR) versus Thermal Compression Bonding with Non-Conductive Paste (TCBNCP)) and with two kinds of substrate formats (singulated unit versus strip form) to investigate the package warpage performance. Interestingly, the results of package warpage were shown different performances on different substrate formats by TCBNCP process only. In this paper, we will present the coplanarity and shadow moiré data as well as mechanism on warpage behavior by different bonding process on both substrate formats from assembly perspective.