FEOL reliability

For modem VLSI, continuous gate oxide thickness scaling poses significant Front-End-of the Line (FEOL) reliability challenges. For instance, Time-Dependent Dielectric Breakdown (TDDB) and Hot-Carrier Injection (HCI) were the most dominant intrinsic FEOL failure mechanisms in traditional CMOS devices. Negative Bias Temperature Instability (NBTI), in additions, had been identified as a significant reliability concern due to dramatic electric field rising in highly scaled technology nodes. To alleviate the rapid gate leakage increases associated with aggressive oxide scaling, High-k dielectric with Metal Gate (HKV MG) has been implemented to replace Si-oxynitride (SiON) with Poly-Si. Besides, new architecture, as the three-dimensional FinFET, was invented to abate short channel effects. Those evolutions led to new reliability concerns, such as Positive Bias Temperature Instability (PBTI) and Stress-Induced Leakage Current (SILC). Here the topic includes an overview of key FEOL reliability challenges, status, and the corresponding learning nowadays. To address the physics, several characterizations such as polarity dependence onBTI and SILC in relation to HK/MG devices are discussed. Finally, future challenges and opportunity for FinFET reliability are also introduced.