Memory efficient implementation of self-corrected min-sum LDPC decoder

This paper proposes memory efficient FPGA implementations for layered quasi-cyclic (QC) LDPC decoders, based on the Self-Correcting Min-Sum (SCMS) algorithm. We address the problem of high memory overhead required by layered SCMS based decoders compared to conventional Min-Sum (MS), by proposing two improvements. These require changes in the flow/rule of the conventional SCMS algorithm, in order to avoid storing the signs and the erasure bits of the variable node messages. Three layered LDPC decoders with serial a-posteriori log likelihood ratios (AP-LLR) processing have been implemented: (1) conventional SCMS, (2) SCMS with no check node message signs storage, and (3) SCMS with neither check node message signs nor erasure bits storage. FPGA implementation results for WiMAX (1152, 2304) code show that the third architecture has a resource utilization with 17% less with respect to the one implementing conventional SCMS, and with 11% less than the second architecture. Furthermore, it presents a similar cost to conventional MS, while having a 0.5 dB better error correction capability.