DocumentCode
3568784
Title
CMOS: a paradigm for low power wireless?
Author
Steyaert, Michiel ; Vancorenland, Peter
Author_Institution
Katholieke Univ., Leuven, Heverlee, Belgium
fYear
2002
fDate
6/24/1905 12:00:00 AM
Firstpage
836
Lastpage
841
Abstract
An overview and comparison of different topologies for wireless architectures are discussed, where the main focus lies on the power consumption and possibilities towards integration and reduction of external components. Architectures with reduced number of building blocks (both internal and external) are presented where the main benefits are the low costs, both in the CMOS technology as well as the power.
Keywords
CMOS integrated circuits; low-power electronics; radio receivers; CMOS technology; low power wireless architecture; power consumption; receiver topology; CMOS technology; Circuits; Costs; Energy consumption; GSM; Impedance; Permission; Radio frequency; Telephone sets; Topology;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2002. Proceedings. 39th
ISSN
0738-100X
Print_ISBN
1-58113-461-4
Type
conf
DOI
10.1109/DAC.2002.1012738
Filename
1012738
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