Enhanced fault-tolerant CMOS memory elements

CMOS memory elements used in space as well as some terrestrial applications must be immune to radiation-induced errors such as single event upsets. Existing designs protect the stored data against single event upsets in the internal nodes, but are vulnerable to transient faults in the control and data lines. In this paper, we enhance the design of a fault-tolerant CMOS latch to handle these types of errors. We propose separate optimizations for pipeline registers and static random-access memories. The designs are verified through extensive circuit simulations.