Title :
Implementations of a hardware n choose k counter
Author :
Nakano, Koji ; Yamagis, Youhei
Author_Institution :
Sch. of Eng., Hiroshima Univ., Japan
Abstract :
The main contribution of this work is to present several hardware implementations of an "n choose k" counter (C (n, k) counter for short), which lists all n-bit numbers with (n-k) 0\´s and k 1\´s. We first present concepts of C (n, k) counters and their efficient implementations on an FPGA. We then go on to evaluate their performance in terms of the number of used slices and the clock frequency for the Xilinx VirtexII family FPGA XC2V3000-4. The best implementations run in 100 MHz for n=16, and in 40 MHz for n=1024.
Keywords :
circuit simulation; field programmable gate arrays; logic design; logic simulation; 100 MHz; 40 MHz; Xilinix ISE logic design tool; Xilinx VirtexII family FPGA XC2V3000-4; hardware implementation; n choose k counter; Clocks; Counting circuits; Field programmable gate arrays; Frequency; Hardware;
Conference_Titel :
Circuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest Symposium on
Print_ISBN :
0-7803-8346-X
DOI :
10.1109/MWSCAS.2004.1354047
