DocumentCode
3569211
Title
Implementation of cell array neuro-processor by using FPGA
Author
Hatano, Fumihiro ; Akita, Noriko ; Komoku, Kiyotaka ; Morishita, Takayuki ; Teramoto, Iwao
Author_Institution
Fac. of Comput. Sci. & Syst. Eng., Okayama Prefectural Univ., Japan
Volume
4
fYear
1999
fDate
6/21/1905 12:00:00 AM
Firstpage
2447
Abstract
We have been studying the neuro-processor that is reconfigured according to needs. We propose an architecture and examine the components of this processor. We implement this processor by using FPGAs. We design this processor by a hardware description language (HDL) and prepare the components to satisfy the architecture
Keywords
adders; field programmable gate arrays; hardware description languages; neural nets; FPGA; cell array neuro-processor; hardware description language; Circuits; Computer architecture; Field programmable gate arrays; Hardware design languages; Large scale integration; Logic arrays; Neural networks; Principal component analysis; Registers; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Neural Networks, 1999. IJCNN '99. International Joint Conference on
ISSN
1098-7576
Print_ISBN
0-7803-5529-6
Type
conf
DOI
10.1109/IJCNN.1999.833454
Filename
833454
Link To Document