Using high-level synthesis to build memory and datapath optimized DSP accelerators

High-Level Synthesis (HLS) has been a hot research topic for more than 30 years. During this long period, HLS has found many enthusiasts and also critics as well. Both of them have presented a lot of arguments for and against, which have helped HLS mature a lot. Modern HLS environments are not restricted to heuristic optimizations of abstract functional blocks (adders and multipliers) as early approaches where, but are supported by rich, technology characterized component libraries, are integrated with other tool flows for simulation, synthesis, verification and prototyping, and their output can be efficiently installed in advanced multicore System-on-Chip (SoC) architectures. As a consequence, the optimization objectives are no longer only the number of abstract components, but technology dependent real implementation measurements, taken in a fast and accurate manner. In this paper, a modern HLS environment is used to investigate different architecture alternatives for the design of Digital Signal Processing (DSP) hardware accelerators, taking into account both memory and datapath component utilization, as well as SoC connectivity opportunities. The whole investigation is performed at the algorithmic level, using algorithmic constructs and directives to describe different architectural options in an abstract yet precise and high productive way. Experimental results show that correct architectural option selections can lead to more than 100X speedup, with little (practical negligible) resource utilization overhead.