Exploiting the behavior of ready instructions for power benefits in a dynamically scheduled embedded processor

Many instructions in a dynamically scheduled superscalar processor spend a significant time in the instruction window (IW) waiting to be selected even though their dependencies are satisfied. These "delays" are due to resource constraints and the oldest first selection policy used in many processors that gives a higher priority to older ready instructions than younger ones. In this paper, we study the "delay" and criticality characteristics of instructions based on their readiness during dispatch. We observe that most ready-on-dispatch (ROD) instructions are non critical and show that 57% of these instructions spend more than 1 cycle in the IW. We analyze the impact of: (i) steering ROD instructions to slow low power functional units; and (ii) early issue of ROD instructions, on power and performance. We find that the "early issue and slow execution" of ROD instructions reduces power consumption by 4-12% while degrading performance by about 5%. On the other hand, "early issue normal execution" of ROD instructions results in 3.5% power savings with less than 1% performance loss. Further, we find that the above policies reduce the energy expended in executing wrong path instructions by about 2%.