A novel dichotomic programming algorithm applied to 3D NAND flash

We introduce a novel programming algorithm that is particularly suitable for 3D NAND. With larger design rules and charge trapping (CT) device 3D NAND is much less sensitive to interference therefore should not use elaborate and costly algorithms designed for scaled 2D NAND. By binary division of cell Vt into smaller groups the number of verification pulses can be reduced. For MLC/TLC which requires large number of verification this can reduce the program time substantially. The algorithm is applied to a VG 3D NAND, and program noise and RTN are carefully studied and their impacts incorporated. An optimized dichotomic ISPP method is designed and tight and efficient MLC/TLC programming demonstrated.