Title :
Isomorphic structured synthesis of Half Adder and Full Adder
Author :
Ghaznavi-Ghoushchi, M.B. ; Nabavi, A.R.
Author_Institution :
Sch. of Eng., Tarbiat Modares Univ., Tehran, Iran
fDate :
6/24/1905 12:00:00 AM
Abstract :
In this paper we present a new method for synthesis of Half Adder (H.A.) and Full Adder (F.A) Units. The synthesis is based on Graph Oriented Realization (GOR). GOR uses BDD and generates another graph called Cut Set Graph. This graph is then simplified and compiled for technology mapping. In the synthesized circuits, we show that there is an isomorphism between 2-input´s AND (Carry) with 2-input´s XOR (Sum) in H.A. and between 3-input´s (Carry) with 3-input´s XOR (Sum). Level Restoration is accomplished by output drivers. Each unit is simulated by HSPICE.
Keywords :
adders; binary decision diagrams; high level synthesis; Cut Set Graph; Full Adder; Graph Oriented Realization; I-layAdder; architecture; binary arithmetic; binary decision diagram; graph isomorphism; synthesis; technology mapping; Adders; Arithmetic; Binary decision diagrams; Circuit simulation; Circuit synthesis; Digital signal processors; Integrated circuit synthesis; Microprocessors; Signal restoration; Signal synthesis;
Conference_Titel :
Electrical and Computer Engineering, 2002. IEEE CCECE 2002. Canadian Conference on
Print_ISBN :
0-7803-7514-9
DOI :
10.1109/CCECE.2002.1013015
