A graph partitioning problem for multiple-chip design

Author

Ting-Chi Wang ; Wong, Derek

fYear

1993

Firstpage

1778

Lastpage

1781

Keywords

Adders; Costs; Design automation; Flow graphs; Integrated circuit interconnections; Law; Legal factors; Libraries;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on

Print_ISBN

0-7803-1281-3

Type

Filename

693014

Link To Document