Noise reduction in analog to digital converters

The critical element in digital signal processing circuits is the analog to digital converter (ADC). The trend is to push up their operating speeds. For a given ADC, theoretically, a given signal to noise ratio (SNR) and dynamic range can be realised. The ADC performance in a practical circuit is likely to deteriorate due to several contributory factors, which raise the noise levels at the input and hence the output of the ADC. This noise level increases with the increase in the operating speeds. If the circuit principles to peg this noise down are not incorporated in the realised circuit, the expected performance from the ADC may not be available, specifically at high speeds of operation. This paper brings out the contributing factors to the noise, suggests techniques to minimize this noise in an ADC circuit and presents the salient parameters of a working high speed ADC circuit incorporating these techniques.