Fast IP packet classification with configurable processor

The next generation IP routers/switches need to provide quality of service (QoS) guarantees and differentiated services. These capabilities require a packet to be classified according to multiple fields in order to determine which flow an incoming packet belongs to. We present a way of achieving fast IP packet classification with a configurable processor as a more flexible and future proof alternative to using a hard-wired ASIC. Configurable processors can be tuned by the system designer with new instructions and hardware. To accelerate table lookups and bitmap manipulation, we develop several customized instructions that are specially optimized to yield large performance improvements. It is shown that one packet needs 16 cycles in the case of cache hit and 30 cycles in the worst case of cache miss for multiple field classification (compared to hundreds of cycles for a standard RISC processor). Thus, it is demonstrated that by using two 200 MHz processors with a proper configuration, OC48 wire-speed packet classification can be achieved while matching multiple fields with sophisticated rules of ranges and/or prefixes