The Correlation between ESD Robustness and Design Parameters in Submicron CMOS Technology

In this paper, we present correlation between the electrostatic discharge (ESD) robustness and the design parameter that is related to the activation of parasitic bipolar junction transistor in submicron CMOS technology. In experiment, we verified the effect of design parameter on ESD immunity, and that each design parameter has a different correlation coefficient depending on the ESD model by statistical analyses. We expect that these analytical results are used to optimize the protection device and to design the novel ESD protection device in deep submicon CMOS process.