An potential and accommodative FIR filter layout hardware implementation using verilog

This paper proposes the architecture of a Finite Impulse Response Filter which is used in many fields of digital signal processing and in very large scale integrated circuits. In the existing system the area complexity of the FIR filter is high. Due to the complexity in area, the power consumption of the components is also increased All these limitations are solved in the proposed system. The main aim of the proposed system is to reduce the area of the finite impulse response filter. The FIR filter computations are based on distributed arithmetic. The size is decreased by reducing the transistor count.