Design and implementation of single electron transistor N-BIT multiplier

Author

Raut, Vaishali ; Dakhole, P.K.

Author_Institution

Electron. & Telecommun. Dept., G.H. Raisoni Coll. of Eng. & Manage., Pune, India

fYear

2014

Firstpage

1099

Lastpage

1104

Abstract

The ancient method of multiplication with low power device i.e. Single electron transistor is used for designing is presented in this paper. SET which is low power device is used to produce new innovations, which is not possible to achieve with only CMOS circuit. The very innovative & simple method of multiplication is presented. By this method of multiplication, n-bit multiplication becomes simple with low power. The basic & circuits required for this design i.e. AND Gate, Half Adder, Full Adder is designed & simulated. 3-bit Multiplier is designed & simulated. For simulation a Spice is used. The logical operation of 3-bit multiplier is explained & verified theoretically as well as by simulation. The Single Electron Transistors is nano device and have less power consumption as compared to CMOS.

Keywords

logic design; low-power electronics; multiplying circuits; single electron transistors; 3bit Multiplier; AND gate; CMOS circuit; SET nanodevice; Spice; full adder; half adder; low power device; n-bit multiplication; single electron transistor N-BIT multiplier; Adders; CMOS integrated circuits; Computers; Integrated circuit modeling; Logic gates; Single electron transistors; Transistors; CMOS; Coulomb blockade; SPICE; single-electron transistor;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuit, Power and Computing Technologies (ICCPCT), 2014 International Conference on

Print_ISBN

978-1-4799-2395-3

Type

conf

DOI

10.1109/ICCPCT.2014.7054930

Filename

7054930