Design of low power stable SRAM cell

The power consumption (Static power, dynamic power) and stability (noise margin) are the major concern areas of today´s CMOS technology. Although various approaches have been developed to reduce the power dissipation, one of the most adopted approaches to reduce the static power dissipation is to reduce the supply voltage in standby mode, that technique has been implemented in this paper. In this paper we present a novel nine transistors SRAM cell to reduce the static power and total power dissipation. When compared to basic conventional six transistors SRAM cell, the proposed SRAM cell shows 81.82% reduction in total power dissipation, where stability is almost same as compare to the conventional six transistors SRAM cell. The proposed SRAM cell uses three extra transistors to reduce the supply voltage during standby mode of SRAM cell and increase the ground voltage during read and write operation of cell. Tanner tools are used for simulation with 250-nm CMOS technology.