Bounding the Worst-Case Execution Time of Static NUCA Caches

Large on-chip caches with uniform access time are inefficient to be used in multicore processors due to the increasing wire delays across the chip. The Non-Uniform Cache Architecture (NUCA) is proved to be effective to solve the problem of the increasing wire delays in multicore processors. For real-time systems that use multicore processors, it is crucial to bound the worst-case execution time (WCET) accurately and safely. In this paper, we develop a WCET analysis approach to consider the effects of static NUCA caches on WCET.