Parallel Subcircuit Extraction Algorithm on GPGPUs

Author

Che Lun Hung ; Hsiao Hsi Wang ; Chun Ting Fu ; Chia Shin Ou

Author_Institution

Dept. of Comput. Sci. & Commun. Eng., Providence Univ., Taichung, Taiwan

fYear

2014

Firstpage

1248

Lastpage

1252

Abstract

Subcircuit Extraction plays an important role in Computer-Aided-Design of digital circuits. With the rapid growth of wafer processing technologies, the integration is from very large scale to giga large scale. Therefore, to extract sub circuits from such large scale integration is computation-consuming problem. In this paper, we propose a parallel sub circuit extraction algorithm on graphic processing unit. The experimental result shows that the proposed algorithm can achieve over 3x-7x times faster than serial algorithm.

Keywords

circuit CAD; graphics processing units; integrated circuit design; parallel algorithms; semiconductor technology; wafer-scale integration; GPGPU; computation-consuming problem; computer-aided-design; digital circuits; general propose graphic processing units; giga large scale; parallel subcircuit extraction algorithm; very large scale; wafer processing technologies; Algorithm design and analysis; Filtering algorithms; Graphics processing units; Heuristic algorithms; Instruction sets; Logic gates; Transistors; Formatting; insert; style; styling;

fLanguage

English

Publisher

ieee

Conference_Titel

High Performance Computing and Communications, 2014 IEEE 6th Intl Symp on Cyberspace Safety and Security, 2014 IEEE 11th Intl Conf on Embedded Software and Syst (HPCC,CSS,ICESS), 2014 IEEE Intl Conf on

Print_ISBN

978-1-4799-6122-1

Type

conf

DOI

10.1109/HPCC.2014.202

Filename

7056902