DocumentCode
357525
Title
IP reuse in the system on a chip era
Author
Savage, Warren ; Chilton, John ; Camposano, Raul
Author_Institution
Synopsys Inc., Mountain View, CA, USA
fYear
2000
fDate
2000
Firstpage
2
Lastpage
7
Abstract
Intellectual property (IP) reuse is one of the keys for system on a chip (SoC) design productivity improvement. Although IP reuse has been explored both technically and as a business for many years, only recently systematic approaches based on EDA technology are starting to emerge in the marketplace. We give an introduction to IP creation, IP conversion and the necessary infrastructure. We address the technical challenges and show that a strict quality based design methodology is the cornerstone to IP reuse. We end with a brief overview of the current marketplace and an outlook of where the industry may go
Keywords
hardware description languages; industrial property; logic CAD; EDA; VHDL; design productivity improvement; intellectual property reuse; quality based design methodology; system on a chip; Automotive engineering; Design engineering; Electrical equipment industry; Electronics industry; Industrial control; Process control; Production facilities; Project management; Quality management; Systems engineering and theory;
fLanguage
English
Publisher
ieee
Conference_Titel
System Synthesis, 2000. Proceedings. The 13th International Symposium on
Conference_Location
Madrid
ISSN
1080-1820
Print_ISBN
0-7695-0765-4
Type
conf
DOI
10.1109/ISSS.2000.874022
Filename
874022
Link To Document