A scaling of cell area with perpendicular STT-MRAM cells as an embedded memory

This paper describes a scaling of MRAM cell area with advanced high performance CMOS technology. The cell area scalability for the cache memory considering MTJ resistivity, switching current, and drive current of access transistor are demonstrated. We consider the layout that the gate pitches are pinned at 3F to 4F. In order to minimize MRAM cell area, it indicates that MTJ resistivity and switching current are the most important factor. Novel scalability of memory cell size with CMOS technology node can be performed with advanced MTJ technology.