DocumentCode :
3578031
Title :
Investigation on Hot-Carrier-Induced degradation of LDMOS transistor fabricated in logic CMOS process
Author :
Huixiong Zheng ; Huaqiang Wu ; Bin Wang
Author_Institution :
Inst. of Microelectron., Tsinghua Univ., Beijing, China
fYear :
2014
Firstpage :
1
Lastpage :
2
Abstract :
Hot-Carrier-Induced linear region drain current degradation is investigated to understand dependence of new parameters Lsub and Lw using LDMOS transistor in 0.18 μm standard CMOS logic process. Results and TCAD simulation show critical role in design rule of those parameters and their optimization.
Keywords :
CMOS logic circuits; MOSFET; hot carriers; logic design; technology CAD (electronics); CMOS logic; LDMOS transistor; TCAD simulation; hot-carrier-induced linear region drain current degradation; size 0.18 mum; Optimization; HCI degradation; LDMOS; graded-junction; logic CMOS; reliability;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices and Solid-State Circuits (EDSSC), 2014 IEEE International Conference on
Type :
conf
DOI :
10.1109/EDSSC.2014.7061107
Filename :
7061107
Link To Document :
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