Title :
Area-efficient recursive degree computationless modified Euclid´s architecture for Reed-Solomon Decoder
Author :
Wen Guo ; Weixin Gai
Author_Institution :
Inst. of Microelectron., Peking Univ., Beijing, China
Abstract :
This paper proposes a high-speed low-complexity simplified recursive degree computationless modified Euclid´s (SrDCME) architecture for the Reed-Solomon Decoder. The area-efficiency of the proposed architecture is obtained by replacing the conventional systolic architecture with a recursive architecture that uses a single processing element. The hardware complexity was further reduced by merging the redundant data paths and introducing new control mechanism. The critical path delay of the proposed SrDCME requires only TMult+TADD and the latency is 4t2-2t which is the lowest compared with previous recursive architectures. The proposed SrDCME architecture has been implemented with 0.13-μm CMOS technology and the synthesized results show that it requires about 24.2% fewer gates than the latest area-efficient design.
Keywords :
Reed-Solomon codes; decoding; CMOS technology; Euclid´s SrDCME architecture; Reed-Solomon decoder; area efficient recursive degree computationless; conventional systolic architecture; critical path delay; hardware complexity; recursive architecture; single processing element; Adders; Computer architecture; Decoding; Hardware; Logic gates; Multiplexing; Satellite communication; Reed-Solomon codes; degree computationless; error correction; modified Euclidean (ME) algorithm;
Conference_Titel :
Electron Devices and Solid-State Circuits (EDSSC), 2014 IEEE International Conference on
DOI :
10.1109/EDSSC.2014.7061134