Title :
A clock circuit for high speed and high resolution pipeline ADC
Author :
Yong Zhang ; Yaling Li ; Ting Li
Author_Institution :
Sichuan Inst. of Solid State Circuits, Chongqing, China
Abstract :
A clock circuit for high speed and high resolution pipelined analog-to-digital conversion is presented. Double duty cycle stabilizers are proposed in the clock circuit, easing the first stage residue amplifier design; A new design method that minimizes the sampling clock jitter is applied in input clock preamplifier.
Keywords :
analogue-digital conversion; preamplifiers; analog-to-digital conversion; clock circuit; double-duty cycle stabilizers; first stage residue amplifier design; high-resolution pipeline ADC; high-speed pipeline ADC; input clock preamplifier; sampling clock jitter minimization; Delays; Integrated circuit modeling; Jitter; Load modeling; ADC; duty cycle stabilizer; jitter; pipeline;
Conference_Titel :
Electron Devices and Solid-State Circuits (EDSSC), 2014 IEEE International Conference on
DOI :
10.1109/EDSSC.2014.7061147
