Impact of Underlap Channel and Body Thickness on the Performance of DG-MOSFET with Si3N4 spacer

In this paper, we investigate the impact of underlap channel, affecting the performance of 20 nm channel length Schottky barrier (SB) double-gate metal-oxide-semiconductor field-effect-transistors (SB-DGMOSFETs) using 2D ATLAS TCAD simulation. For this purpose, we proposed an asymmetric underlap channel double gate (DG) SB-MOSFETs with Si₃N₄ spacer layer. Simulation of major device performance metrics such as on-state current (I_ON), off-state current (I_OFF), subthreshold slope (SS), threshold voltage (V_th), and associated capacitance variation gate-to source capacitance (C_GS), gate-to-drain capacitance (C_GD) have been done for substrate thickness (T_Si) ranging from 6nm to 10nm. It has been found that by employing underlap channel there is improvement in I_ON, reduction in I_OFF & ambipolar leakage current. However, the reduction in ambipolar behavior is also observed, due to reduced effective gate voltage across the underlap channel length.