Towards power efficient wireless NoC router for SOC

With the Continuous advancement of technology, enormous amount of heterogeneous devices can be integrated on a single chip in an efficient manner. It implies the need of high performance routers to communicate between the devices. For achieving high speed communication, the interconnection between the multiple cores should be an efficient one. In this paper, we expose a new architecture for an efficient low power wireless network on chip router which can be integrated within the System on Chip. The Interconnect fabric router architecture is designed through VHDL and simulated using Xilinx.