A 8-bit 10MS/s asynchronous SAR ADC with resistor-capacitor array DAC

This paper presents a 65nm 8-bit 10MS/s asynchronous successive approximation register analog to digital converter (SAR ADC). This SAR ADC adopts resistor-capacitor array digital to analog converter (DAC) that has more advantages than only resistors or capacitors. This kind of DAC reduces the capacitance area, while ensuring that the DAC processes good integral nonlinearity and differential nonlinearity. In addition, the design uses asynchronous sequential logic control to ensure that SAR ADC regular operates by the feedback signals from comparator when comparison is completed, avoiding the application of high-speed clock. In terms of both power and speed, it can be very good improvement. This design uses the SMIC 65nm CMOS process, simulation results indicate that at 10MS/s sampling frequency, which is Nyquist sampling, with analog power of 2.5V and digital power of 1.2V, the maximum integral nonlinearity error is 0.8LSB, the maximum differential nonlinearity error is 0.5LSB and ENOB is up to 7.8bit.