Implementation for Multiplying IEEE 754-2008 Binary 32 Bit Number Using Verilog

The main aim of this paper is to design a parameterized 32 bit floating point multiplier which is based on IEEE 754-2008 binary interchange format. The proposed work is capable of checking overflow and underflow using corresponding flags by flagger circuit. In this design rounding modes are also considered based on the two bit control signal provided as input such as round to nearest even, round to zero, round to positive infinity and round to negative infinity for better accuracy of output result. The delay summary report generated presents a chart of some of the delay list in implementing the design, the numbers of signals are completely routed in this design. The total gate delay is 22.94ns. The xpower analyzer tool is used to calculate power of this implemented design which comes out to be 34mw. The proposed design of floating point multiplier format is implemented on Xilinx virtex-6, Xp6gls240t family, 40 nm technology, which is having top level source as HDL, the synthesis tool used is XST (Verilog/Vhdl), and the preferred language is Verilog. The core is verified against Xilinx floating point multiplier and simulation has been done on unified ISE simulator.