Development of a Field programmable GATE array based computer to controller area network store and forward buffer

In this paper the development of a Field programmable Gate Array (FPGA) based general purpose computer to Controller Area Network (CAN) store and forward buffer is being discussed. This buffer will read from the incoming data from the computer as bytes and collect and combine them to form the CAN frame and post it to the CAN network for transmission. In the process of development, CAN message frame architecture, voltage levels and bit coding principles were studied extensively. For the experiments and implementation of the designed buffer a developer board with Xilinx Spartan 3E FPGA which has 1920 Configurable Logic Blocks (CLB) was used. Computer to FPGA communications is carried out using RS-232 serial communications. 136 bit long CAN frame is built on the computer and separated to 17 bytes and forwarded to the FPGA. The FPGA assembles it and posts the frame to the network. In this implementation, from the available total, 315 flip flops and 569 look up tables (LUT) were used. From these 443 were used as logic, 126 were used as route through and 1 was used as a shift register. Since the usage of the RS-232 protocol a communication bottleneck makes rise to a delay of 14.1667 ms per frame sent from computer to the FPGA. This delay can be reduced by using Universal Serial Bus (USB) protocols to communicate with the computer. Even though this implementation is for the low speed fault tolerant CAN, speeds can be customized to suit the requirement by varying the frequency of clock ticks, given that the hardware supports such frequencies. As further research this store and forward buffer can be improved to receive acknowledgments from other nodes of the network.