VHDL-based implementations of area and power efficient filter architectures

Digital signal processing operations, e.g., digital filters, are one important class of application in communication devices. A digital filtering algorithm can be implemented in various ways by selecting one architecture from the set of possible realizations. By choosing an advanced architecture notable advantages in both the silicon area and power dissipation can be achieved compared to the conventional direct-form realization. This paper focuses on interpolated finite impulse response (interpolated FIR) filter and recursive running-sum (RRS) filter based architectures. The VHDL-based implementations prove that these advanced architectures are efficient when low-power or low-area characteristics are desired. Over 55 percent savings in the area and in the power dissipation were achieved when an FIR filter with a narrow transition band was implemented using these architectures.