Low power challenge and solution for advanced mobile device design

With CMOS technology scaled down, leakage power becomes one of the most important design concerns for mobile device. In this paper, low power and leakage reduction methods in industry for 28nm CMOS technology are introduced. The methodologies which will be discussed include long poly cell ratio optimization, ultralow Vt (threshold voltage) cell ratio optimization, power switch cell insertion, daisy chain number optimization, voltage scaling as well as power island optimization. The advantages and design overhead of these approaches will be discussed as well.