• DocumentCode
    3586282
  • Title

    Recent advances in ASIC-compatible circuit techniques for a SOC in newly emerging application areas: Invited paper

  • Author

    Dhong, Sang H. ; Wei Hwang

  • Author_Institution
    Dept. of Electron. Eng., Nat. Chiao-Tung Univ., Hsinchu, Taiwan
  • fYear
    2014
  • Firstpage
    24
  • Lastpage
    25
  • Abstract
    We review advances in ASIC-compatible circuits for emerging SOC areas. These applications require ubiquitously low-power consumption during standby mode while providing a required performance in active mode. Sub- or near-threshold circuits may provide a low-power solution. However, they have yet to show how they fit into overall SOC optimization including area and performance. Selectively introducing custom-circuit techniques with ASIC tool compatibility have proven very attractive in reducing both the power and the area of a SOC by extending its Dynamic Voltage-Frequency Scaling (DVFS) range down to a VDD of 0.5 V.
  • Keywords
    application specific integrated circuits; system-on-chip; ASIC tool compatibility; ASIC-compatible circuit techniques; SOC; active mode; dynamic voltage-frequency scaling range; low-power consumption; standby mode; voltage 0.5 V; Clocks; Logic gates; System-on-chip; Timing; 0.5V VDD; ASIC; DVFS; IOT; Pulse latch; SOC;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SoC Design Conference (ISOCC), 2014 International
  • Type

    conf

  • DOI
    10.1109/ISOCC.2014.7087566
  • Filename
    7087566