A low power high linearity phase interpolator design for high speed IO interfaces

In clock and data recovery system of high speed IO, the phase of the clock for data sampler needs fine resolution control so that the incoming data can be sampled at a time point with the best signal-to-noise ratio. A phase interpolator (PI) is normally used as a phase shifter (or phase rotator) to generate an output clock whose phase is precisely controlled. In this paper we present a novel control code generation algorithm which can improve the linearity of PI without increasing the complexity of analog circuit used in linearly coded PI.