SEU-tolerant active body-bias inverter

PD-SOI (Partial Depleted Silicon On Insulator) process is a good candidate technology for space system designs, since it features excellent insulation to the silicon substrate compared to the conventional bulk process. However, the radioactive particles from the low earth orbit can causes the single event upset (SEU) or the charge collection in a circuit node, leading to a logical error. We propose SEU-tolerant CMOS logic inverter using a novel active body-bias scheme.