Title :
A 10-bit 20-MS/s asynchronous SAR ADC with controllable analog input voltage range and meta-stability detection circuit
Author :
Sang-Min Park ; Yeon-Ho Jeong ; Dong-Gil Jeong ; Seung-Wuk Baek ; Yu-Jeong Hwang ; Pil-Ho Lee ; Young-Chan Jang
Author_Institution :
Dept. of Electron. Eng., Kumoh Nat. Inst. of Technol., Gumi, South Korea
Abstract :
A 10-bit 20-MS/s asynchronous SAR ADC, which has a controllable analog input voltage range and a meta-stability detection circuit, is proposed. The proposed SAR ADC with the area of 0.095 mm2 is implemented using a 130-nm CMOS process with 1.2-V supply. The measured peak ENOBs for the full rail-to-rail ±1.2V (peak-to-peak) differential sinusoidal input signal is 9.56 bits. The FoM achieves 41 fJ/conversion-step.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; asynchronous circuits; circuit stability; detector circuits; flip-flops; integrated circuit measurement; logic design; voltage control; CMOS process; ENOB; FoM; analog-to-digital converter; asynchronous SAR ADC; controllable analog input voltage range; differential sinusoidal input signal; effective number of bits; figure of merit; metastability detection circuit; size 0.095 mm; size 130 nm; successive approximation register; voltage 1.2 V; Capacitors; Switches; analog-to-digital converter; asynchronous successive approximation register; half rail-to-rail analog input range;
Conference_Titel :
SoC Design Conference (ISOCC), 2014 International
DOI :
10.1109/ISOCC.2014.7087654
