Design of a near-threshold digital LDO with fast transient response

Author

Yunsheng Chan ; Yingchieh Ho

Author_Institution

Dept. of Electr. Eng., Nat. Dong-Hwa Univ., Taiwan

fYear

2014

Firstpage

136

Lastpage

137

Abstract

A near-threshold digital LDO (DLDO) with fast transient response is presented in this paper. In order to improve settling time, a voltage-controlled delay line (VCDL) with a new proposed delay cell is developed to enhance conversion gain. In addition, Vernier-delay-line-based time-to-digital convertor (TDC) is used to quantize phase from phase frequency detector (PFD). Furthermore, digital coarse and fine tunings are developed to control PMOS array. The test chip is designed in 90nm SPRVT CMOS and operates at 0.3-0.5V with output voltage of 0.25-0.45V. Simulation results show that current efficiency at 2.8mA is 99.6%. The settling time is only 8us and 12us when load current I_LOAD is 200uA and 2.8mA, respectively.

Keywords

CMOS digital integrated circuits; delay lines; integrated circuit design; time-digital conversion; transient response; PFD; PMOS array; SPRVT CMOS; VCDL; Vernier-delay-line-based TDC; Vernier-delay-line-based time-to-digital convertor; conversion gain; current 2.8 mA; current 200 muA; current efficiency; delay cell; digital coarse tuning; efficiency 99.6 percent; fast-transient response; fine tuning; near-threshold DLDO; near-threshold digital LDO design; phase frequency detector; phase quantization; settling time; time 12 mus; time 8 mus; voltage 0.3 V to 0.5 V; voltage-controlled delay line; Delays; Frequency conversion; Loading; MOS devices; Noise; Regulators; Resistors; Digital LDO; time-to-digital converter; voltage control delay line;

fLanguage

English

Publisher

ieee

Conference_Titel

SoC Design Conference (ISOCC), 2014 International

Type

conf

DOI

10.1109/ISOCC.2014.7087665

Filename

7087665