A systematic procedure for deriving block-parallel, power efficient, digital filter architectures for highspeed data conversion

A systematic and highly intuitive procedure for deriving the digital filter realization of an arbitrary block-parallel and/or pipelined discrete-time transfer function H(z) is proposed. The method is based on simple block diagram and multi-rate (filter-bank) properties and is intended for low-power processing by reducing (a) the required system clock frequency and (b) the number of required multipliers by facilitating arithmetic resource sharing. We provide design examples for (classical) direct-form FIR and IIR filters as well as for specialized architectures such as fractional-delay Farrow (programmable FIR), lattice-ladder (IIR), Adaptive Phase Equalization (programmable IIR) and Multiplier-less MAXFLAT filters. The technique and examples presented are intended to serve as a high-speed filter realization reference for Digital and DSP ASIC developers.