Hybrid floating-point modules with low area overhead on a fine-grained processing core

Author

Pimentel, Jon J. ; Baas, Bevan M.

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of California, Davis, Davis, CA, USA

fYear

2014

Firstpage

1829

Lastpage

1833

Abstract

This paper proposes Hybrid Floating-Point Modules (HFPMs) as a method to improve software floating-point (FP) throughput without incurring the area overhead of hardware floating-point units (FPUs). The proposed HFPMs were synthesized in 65 nm CMOS. They increase throughput over a fixed-point software FP implementation by 3.6× for addition/subtraction, 2.3× for multiplication, and require less area than hardware modules. Nine functionally equivalent FPU implementations using combinations of software, hardware, and hybrid modules are synthesized and provide 1.07-3.34× higher throughput than a software FPU implementation, while requiring 1.08-12.5× less area than a hardware FPU for multiply-add operations.

Keywords

CMOS digital integrated circuits; floating point arithmetic; CMOS; FPU; HFPM synthesis; addition operation; fine-grained processing core; fixed-point software FP implementation; hardware FPU; hardware floating-point units; hardware module; hybrid floating-point modules; hybrid module; low-area overhead; multiplication operation; multiply-add operations; size 65 nm; software FP throughput improvement; software floating-point throughput improvement; software module; subtraction operation; CMOS integrated circuits; Computer architecture; Hardware; Program processors; Registers; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems and Computers, 2014 48th Asilomar Conference on

Print_ISBN

978-1-4799-8295-0

Type

conf

DOI

10.1109/ACSSC.2014.7094784

Filename

7094784