• DocumentCode
    3590635
  • Title

    Session 2: Hardware, FPGAs, and reconfigurable hardware

  • Author

    Martin, Kevin

  • Author_Institution
    Hardware, FPGAs, and Reconfigurable Hardware
  • fYear
    2014
  • Firstpage
    1
  • Lastpage
    1
  • Abstract
    Since their first appearance, FPGAs have been widely used, studied, and enhanced. It makes it an attractive component for low-volume devices, for prototyping, and for efficient implementation exploiting its parallelism features. The design on FPGA also relies on methods and tools that improve productivity in a convinient way. In this session, an FPGA implementation of a flexible synchronizer for cognitive radio applications is presented. An FPGA is used for prototyping memory controllers and predictive cache for image processing algorithms. A methodology and tool for automatic generation of data-flow based reconfigurable accelerators is presented and used for MPEG Reconfigurable Video Coding applications. A new soft-core is implemented in a Zynq to show the benefit of offloading operating system services.
  • Keywords
    Cognitive radio; Field programmable gate arrays; Hardware; Operating systems; Parallel processing; Productivity; Synchronization;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design and Architectures for Signal and Image Processing (DASIP), 2014 Conference on
  • Type

    conf

  • DOI
    10.1109/DASIP.2014.7115602
  • Filename
    7115602