HLS-based FPGA implementation of a predictive block-based motion estimation algorithm — A field report

This paper presents the application and evaluation of high-level synthesis (HLS) tools for a complex video processing algorithm. As case study predictive block-based motion estimation is chosen. The hardware implementation of the algorithm is introduced, and the implementation using HLS tools is presented, including various tips and pitfalls. The resulting HLS generated code is compared to a hand-coded version in terms of performance and resource requirements by synthesizing both versions for a Virtex-7 FPGA, and also in terms of implementation time and code length and readability. The results show that the processing performance is comparable and the required resources are acceptable for current FPGAs for an HLS-based implementation. Finally, recommendations are given for which parts of the motion estimation algorithm the HLS-based approach is preferable, and which parts should be implemented manually, allowing a prognosis for further video processing algorithms.