A low-power design technique for digital signal processing applications

Author

Varga, László ; Hosszú, Gábor ; Kovács, Ferenc

Author_Institution

Dept. of Electron Devices, Tech. Univ. Budapest, Hungary

Volume

2

fYear

2000

fDate

2000

Firstpage

827

Abstract

We present a novel design technique to reduce the power consumption of the data paths. Our technique is based on the observation that a circuit can be optimally synthesized for a particular type of inputs. We use logic-level techniques to re-synthesize data path elements to be effective in terms of power dissipation. The regularity of data path elements are destroyed, however, voltage scaling can be applied, which result in power savings.

Keywords

circuit optimisation; combinational circuits; digital signal processing chips; integrated circuit design; logic design; DSP applications; DSP chip; combinational logic; combinational logic block; data path elements synthesis; data paths; digital signal processing applications; input distribution; input vectors; logic-level techniques; low-power design; multiple-level logic optimization; power consumption reduction; power dissipation; power savings; registers; voltage scaling; Capacitance; Circuit synthesis; Design optimization; Digital signal processing; Digital systems; Energy consumption; High level synthesis; Power dissipation; Signal design; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrotechnical Conference, 2000. MELECON 2000. 10th Mediterranean

Print_ISBN

0-7803-6290-X

Type

conf

DOI

10.1109/MELCON.2000.880061

Filename

880061