Title :
A research of high-speed Batcher´s odd-even merging network
Author :
Jun, Yang ; Na, Li ; Jun, Ding ; Yixiong, Guo ; Zuoxi, Tang
Author_Institution :
Sch. of Inf. Sci. & Eng., Yunnan Univ., Kunming, China
Abstract :
Batcher´s odd-even merging network can be easily implemented on hardware. And its parallel working between the comparator is very beneficial to play the advantages of hardware such as high efficiency and high speed. These make it as the most widely used sort algorithm. In this paper, FPGA is used to implement Batcher´s odd-even merging network, solving the problems of traditional design. And the scalability of Batcher´s odd-even merging network is also studied in this paper. The end results show that Batcher´s odd-even merging network can be used to not only sort and classify the data, but also fast complete the parallel data packets distribute.
Keywords :
field programmable gate arrays; hardware description languages; merging; parallel processing; sorting; FPGA; high-speed Batcher odd-even merging network; parallel data packets distribute; Ecosystems; Field programmable gate arrays; Hardware design languages; Information processing; Merging; Packet switching; Parallel processing; Partitioning algorithms; Quaternions; Sorting; Batcher´s odd-even merging network; FPGA; Verilog HDL; high-speed;
Conference_Titel :
E-Health Networking, Digital Ecosystems and Technologies (EDT), 2010 International Conference on
Print_ISBN :
978-1-4244-5514-0
DOI :
10.1109/EDT.2010.5496517
