A novel partially insulated junctionless transistor for low power nanoscale digital integrated circuits

Author

Patil, Ganesh C. ; Bonge, Vijaysinh H. ; Malode, Mayur M. ; Jain, Rahul G.

Author_Institution

Dept. of Electron. & Telecommun. Eng., Savitribai Phule Pune Univ., Pune, India

fYear

2014

Firstpage

1

Lastpage

4

Abstract

In this paper, a novel device structure named as partially insulated (Pi-OX) junctionless transistor (JLT) is proposed and the simulated results below 20 nm have been compared with existing silicon-on-insulator (SOI) JLT. Further, drain-induced barrier lowering (DIBL), subthreshold swing (SS), on-state drive current (I_ON), off-state leakage current (I_OFF), I_ON/I_OFF ratio and static power dissipation (P_STAT) of the proposed Pi-OXJLT and SOIJLT has also been compared. It has been found that, I_OFF, DIBL and SS in the case of proposed Pi-OXJLT are reduced by 57%, 17% and 10% respectively over the existing SOIJLT device. The fabrication flow of the proposed Pi-OXJLT is proposed.

Keywords

digital integrated circuits; field effect transistors; leakage currents; low-power electronics; semiconductor device models; DIBL; device structure; drain-induced barrier lowering; low power nanoscale digital integrated circuits; off-state leakage current; on-state drive current; partially insulated junctionless transistor; static power dissipation; subthreshold swing; Fabrication; Logic gates; MOSFET; Nanoscale devices; Performance evaluation; Silicon; Junctionless transistor; Short channel effects; partially insulated buried oxide; scaling;

fLanguage

English

Publisher

ieee

Conference_Titel

Emerging Electronics (ICEE), 2014 IEEE 2nd International Conference on

Print_ISBN

978-1-4673-6527-7

Type

conf

DOI

10.1109/ICEmElec.2014.7151171

Filename

7151171